Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash memory devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash memory devices enable the erasing of all memory cells in the device using a single current pulse.
In flash memory devices, Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”) memory cells, such as Advanced Micro Devices' (“AMD”) MirrorBit™ memory cell, can be utilized to achieve long data retention, low-voltage operation, and fast programming speed. A SONOS memory cell, such as Advanced Micro Devices' (“AMD”) MirrorBit™ memory cell, includes a polycrystalline silicon (“poly”) gate situated on an Oxide-Nitride-Oxide (“ONO”) stack. The ONO stack is a three layer structure including a bottom oxide layer situated on a substrate, a nitride layer situated over the bottom oxide layer, and a top oxide layer situated over the nitride layer. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO stack. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped and stored in the nitride layer.
In a flash memory cell, such as the SONOS flash memory cell discussed above, threshold voltage (“Vt”), which can be defined as the gate voltage required to obtain a desired source-to-drain current, must be controlled to achieve optimal memory cell performance and power consumption. If Vt is too high, for example, memory cell performance can decrease. One cause of unacceptably high Vt is ultraviolet (“UV”) radiation-induced charge in dielectric areas and layers in and adjacent to the memory cell, such as gate spacers and ONO stack layers. UV radiation-induced charging results from semiconductor fabrication processes that produce UV radiation, such as plasma etching and chemical vapor deposition (“CVD”) processes. When Vt is too high as a result of UV radiation-induced charge, adjusting processing parameters, such as implantation dosage, may not be effective in sufficiently lowering Vt. Thus, UV radiation-induced charge causes decreased Vt control in the memory cell, which decreases memory cell performance.
The UV radiation-induced charge discussed above comprises electrons and holes, which have a high energy as a result of being induced by high-energy UV radiation. As a result, the high-energy electrons and holes induced by the high-energy UV radiation can damage critical layers of the memory cell, such as the bottom oxide layer of the ONO stack, which serves as a “tunnel” for electrons to charge the nitride layer of the ONO stack during memory cell programming. As a result of damage to the bottom oxide layer of the ONO stack caused by UV radiation, memory cell reliability is reduced.
Moreover, due to lack of adequate blocking of reflections (UV or otherwise) in conventional process technologies, critical dimension control of contacts is significantly impaired. It is thus desirable to resolve both the UV radiation and the contact critical dimension control problems. Thus, there is a need in the art for an effective structure to prevent UV radiation from decreasing performance and reliability of a memory cell, such as a SONOS flash memory cell. Moreover, there is a need in the art to exercise better control over contact critical dimension.